1. Field of the Invention
The present invention relates to an enabling-circuit for enabling a momentary test mode of integrated circuits and more particularly to, a momentary test mode enabling circuit for enabling a test mode by use of a negative pulse signal below a ground potential which makes it possible to input a normal operational signal to an input pin during the test mode so that momentary enabling and disabling operations may be carried out.
2. Description of the Prior Art
In general, test mode enabling circuits are used in memory devices and various types of test mode enabling circuits are well known in the art. One conventional test mode enabling circuit is disclosed in U.S. Pat. No. 4,733,168(Blankenship et al.). The conventional test mode enabling circuit, as shown in FIG. 1, comprises a level detecting circuit 2 for detecting a level of an input pin 1, an inverter gate 3 for inverting and buffering the detection signal from the level detecting circuit 2, and a limiting circuit 4 for limiting a maximum and a minimum values of the level being inputted to the input pin 1.
The level detecting circuit 2 is constituted such that a source of an NMOS transistor M1 is connected to the input pin 1 through a resistor R1, the drain and gate of NMOS transistor M1 are connected in common to a source of an NMOS transistor M2, a gate of the NMOS transistor M2 is grounded, the drain of the NMOS transistor M2 is connected in common to an emitter of a bipolar transistor Q1 and a source of an NMOS transistor M3, the drain and gate of the NMOS transistor M3 are connected to a power source V.sub.DD, the base of the bipolar transistor Q1 is grounded, and the collector thereof is connected to a power source V.sub.DD.
The limiting circuit 4 limits the maximum and minimum values of a level being inputted to the input pin 1 so as to protect other peripheral circuits from a surge which may be applied to the input pin 1.
The inverter gate 3 inverts the level of an input signal which is detected at the level detecting circuit 2 so that the indefinite level detection signal of the level detecting circuit 2 may be outputted as a correct high level or low level signal.
Since the gate of the NMOS transistor M2 is grounded, an input signal of a level that threshold voltages 2 V.sub.T of the NMOS transistors M2 and M1 are subtracted from the ground potential has to be applied in order to turn on the NMOS transistors M1 and M2. Also, since the base of the bipolar transistor Q1 is grounded, the minimum value of the potential of a connection node N1 at the emitter side of the bipolar transistor Q1 is limited by the value obtained by subtracting a threshold voltage of the bipolar transistor Q1 from the ground potential.
When the basic conditions of the circuit are determined and the level of the input voltage V.sub.IN being applied to the input pin 1 is in a normal state, that is, the level of the input voltage V.sub.IN is between the ground potential and the Dower source voltage, the NMOS transistors M1 and M2 are in a turn-off state and a voltage of a level V.sub.DD -V.sub.TN is generated at the connection node N1 through the NMOS transistor M3 which is always in a turn-on state, and the voltage is applied to the inverter gate 3. Thus, the output signal of the inverter gate 3 comes to the ground level.
Meanwhile, the level of the input voltage V.sub.IN being applied to the input pin 1 drops down below ground level, the NMOS transistor M1 is turned on so that the electric charges at the connection node are discharged through the NMOS transistor M1.
In other words, when the input level V.sub.IN drops down below GND-V.sub.TN, the NMOS transistor M2 is turned on and the level at the node N1 drops down.
At this moment, when the level at the node N1 drops down to the ground level GND, the voltage between the drain and the source of the NMOS transistor M3 becomes equivalent to the voltage between its gate and source and thus the NMOS transistor M3 becomes saturated.
Accordingly, the level at the node N1 is maintained at the ground level GND and the output of the inverter gate 3 becomes a high level signal, thereby enabling the test mode.
In such a conventional circuit, a lot of power loss occurs due to a static current during the test mode enabling period, and since the high level at the node N1 which is an input of the inverter gates M4 and M5 becomes V.sub.DD -V.sub.TN, the noise margin is insufficient. Also, since the inverter gates are used to detect the level at the node N1, the switching characteristics of the connection node N3 are bad.